FPGA's Architecture Digital Circuit Complex Design Exam. (EXAMPLE) Departamento de Ingeniería Electrónica y Automática. Name: Surname: Warning: for every two wrong answers one correct answer will be deduced Q1. What is the most used technology family to create integrated logic devices nowadays? □1. BiCMOS □2. CMOS □3. ECL Q2. What kind of logic gate is represented by the figure shown below? □1. NAND □2. NOR □3. AND □4. None of them are true A B OUT Q3. What is the meaning of “a full-custom digital integrated circuit”? □1. The integrated circuit was totally assisted by CAD tools and the implementation of the layout of the circuit was a transparent process for the designer. □2. The integrated circuit has digital components and analog ones such as internal power supply references to establish the voltage level at the output. □3. The whole design and layout of the integrated circuit is a “handmade” process developed by the designer □4. Full-custom is referred to the final package used to encapsulate the integrated circuit. Q4. Chose the false sentence related to the PROMs listed below □1. The PROMs can be programmed only once □2. The PROMs are considered the predecessors of the PLD □3. The anti-fuses are the internal elements used to create the internal connections □4. PROMs can be erased applying UV light 1 FPGA's Architecture Digital Circuit Complex Design Exam. (EXAMPLE) Departamento de Ingeniería Electrónica y Automática. Q5. What is the state of the output for the Tri-state device shown below ? □1. 1, high logic level □2. 0, low logic level □3. High impedance □4. Low impedance Input Ouput 1 ? 0 Q6. How does Altera call their logic blocks? □1. Configurable logic blocks (CLBs) □2. SLICEs □3. Logic elements (LEs) □4. Logic array blocks (LABs) Q7. In the image shown below appears the typical structure of a logic block. What is the name of the box indicated by the arrow? □1. Look up table (LUT) □2. D flip-flop (DFF) □3. Full-Adder (FA) □4. Bypass 2 FPGA's Architecture Digital Circuit Complex Design Exam. (EXAMPLE) Departamento de Ingeniería Electrónica y Automática. Q8. What is the logic gate implemented by the LUT shown below? □1. NAND gate □2. XNOR gate □3. NOR gate □4. None of them Q9. Chose the true sentence listed below □1. Xilinx gathers their logic cells in a block called SLICE □2. Xilinx gathers their logic cells in a block called Logic Element □3. None of them are true Q10. The interconnections between global vertical and horizontal lines are made by □1. AND gates □2. anti-fuses □3. pass-transistors □4. None of them are correct 3
